<?xml version="1.0" encoding="UTF-8"?>
<otherdata xmlns="http://linux.duke.edu/metadata/other" packages="9">
<package pkgid="a1e71b654ce39af4a732a00a8e4a42ad02237aa496bf5fc8b2111742a593380dd6e460e9513b234b5616b1e04866bf7a0d88470ea087e4c222164d10d8cab9d5" name="cpuid" arch="i586">
  <version epoch="0" ver="20230614" rel="2.33"/>
  <changelog author="Andreas Stieger &lt;andreas.stieger@gmx.de&gt;" date="1588075200">- update to 20200427:
  * Add synth decoding for AMD Steppe Eagle/Crowned Eagle
    (Puma 2014 G-Series), based on instlatx64 sample
  * Add 7/0/edx SERIALIZE &amp; TSXLDTRK bit descriptions
  * Add 0xf/1/eax Counter width &amp; overflow flag
  * Add 0x10/3/ecx per-thread MBA controls flag
  * Add 0x8000001f fields
  * Add AMD 24594 &amp; 40332 docs
  * Correct field lengths in 14/0 and 14/1 subleafs so that
    columns line up
  * Add CC150 (Coffee Lake R0) synth decoding, based on
    instlatx64 example
  * Add Jasper Lake A0 stepping (from Coreboot*)
  * Update 1/ebx "cpu count" to modern terminology: "maximum
    addressible IDs for CPUs in pkg" to avoid user confusion
  * Update 4/eax CPU &amp; core count terminology in the same way</changelog>
  <changelog author="Josef M&#xF6;llers &lt;josef.moellers@suse.com&gt;" date="1602158400">- Update to 20201006:
  Added "Sapphire Rapids", "Golden Cove", "Rocket Lake", "Cato",
  14nm "Zen", "Tiger Lake-U B0", "Elkhart Lake B0", "Alder Lake",
  "Comet Lake", "Picasso A1", "Renoir A1", "Zhaoxin KaiXian KX-6000",
  as well as some additional decoding of supported features.
  [cpuid-20201006.src.tar.gz, jsc#sle-13189]</changelog>
  <changelog author="Andreas Stieger &lt;andreas.stieger@gmx.de&gt;" date="1636977600">- update to 20211114:
  * Many updated and added identified CPU models and variants
  * Updated hypervisor support</changelog>
  <changelog author="Andreas Stieger &lt;andreas.stieger@gmx.de&gt;" date="1645704000">- update to 20220224:
  * Support for AMD Rembrandt E1
  * Add hypervisor+4/eax (Xen) expanded destination id bit
  * Correction for Alder Lake, Rocket Lake decoding
  * Multiple detection and decodings updated</changelog>
  <changelog author="Jan Engelhardt &lt;jengelh@inai.de&gt;" date="1660392000">- Update to release 20220812
  * Corrected (synth) decoding for (0,6),(8,6) Intel Snow
    Ridge/Parker Ridge.
  * Added 8000000a/edx X2AVIC flag
  * Generalized (0,6),(8,14),9,YP stepping case to include
    Pentium 4425Y, from instlatx64 sample.
  * Added support for hypervisor+3/ecx (Microsoft) flags.</changelog>
  <changelog author="Valentin Lefebvre &lt;valentin.lefebvre@suse.com&gt;" date="1665662400">- Update to release 20221003
  * Added synth decoding for AMD Ryzen (Phoenix E0, Storm Peak A1)
  * Added synth &amp; uarch synth decoding for
  * (0,6),(11,5) Intel Meteor Lake
  * (0,6),(11,6) Intel Grand Ridge (Crestmont)
  * (0,6),(11,14) Intel Granite Rapids
  * Renamed 7/0/eax enh hardware feedback to just "Thread
    Director".
  * Added 7/1/eax instructions.
  * Added 0x12/0/eax SGX ENCLU EDECCSA flag.
  * Added 0x23 Architecture Performance Monitoring Extended leaf
    decoding.
  * Corrected AVX512IFMA description: integer FMA, not just FMA.
- Release 20220927
  * Added synth decoding for (10,15),(6,1) Raphael
  * Fixed title for AMD 0x8000001a leaf: Performance Optimization
    identifiers.</changelog>
  <changelog author="Valentin Lefebvre &lt;valentin.lefebvre@suse.com&gt;" date="1670241600">- Update to release 20221201
  * Clarified synth decoding for Intel Xeon D-1700.
  * Added uarch &amp; synth decoding for AMD 4800S Desktop Kit, based on
    instlatx64 sample.
  * Added uarch decoding for AMD Genoa A1, based on instlatx64 sample
  * Added uarch decoding for (0,6),(12,15) Emerald Rapids, from LX*.
  * Added synth &amp; uarch decoding for (10,15),(10,1) Bergamo.
  * Added 0x8000000a/edx bits: ROGPT, VNMI, IBS virtualization.
  * Added 0x8000001b/eax bit: IBS L3 miss filtering support.
  * Added 0x8000001f/eax bits: RMPQUERY instruction support,
    VMPL supervisor shadow stack support, VMGEXIT parameter support,
    virtual TOM MSR support, IBS virtual support for SEV-ES guests,
    SMT protection support, SVSM communication page MSR support,
    VIRT_RMPUPDATE &amp; VIRT_PSMASH MSR support.
  * Added 0x80000020/0/ecx bit: L3 range reservation support.
  * Added 0x80000021/eax bits: automatic IBRS,
    CPUID disable for non-privileged.
  * Added 0x80000022/eax bit: AMD LBR &amp; PMC freezing.
  * Added 0x80000022/ebx field: number of LBR stack entries.
  * Added 0x80000023 leaf: Multi-Key Encrypted Memory Capabilities.
  * Added 0x80000026 leaf: AMD Extended CPU Topology.
  * cpuid.c: use lseek64 and cpuset_setaffinity, Added 0x80000022/eax
    AMD LBR V2 flag, from LX*.</changelog>
  <changelog author="Dirk M&#xFC;ller &lt;dmueller@suse.com&gt;" date="1674907200">- updated to 20230120:
  * Intel's 13th Generation Core datasheet provides stepping names as
    well as numbers!  So:
  * cpuid.c: Added synth decoding for (0,6),(11,7) Raptor Lake B0 stepping.
  * cpuid.c: Added synth decoding for (0,6),(11,15) Raptor Lake C0
    steppings, and clarified case for unknown stepping.
  * cpuid.man: Added 743844: 13th Generation Core datasheet.
  * cpuid.c: Fixed (0,6)(12,15) synth typo: Emearld Rapids.
  * cpuid.c: Added 6/eax IA32_HW_FEEDBACK_THREAD_CONFIG bit 25.
  * cpuid.c: Added 7/0/edx SGX-KEYS: SGX attestation services.
  * cpuid.c: Clarified 7/0/edx IA32_MCU_OPT_CTRL SRBDS mitigation MSR.
  * cpuid.c: Clarified 7/0/edx IA32_TSX_FORCE_ABORT MSR.
  * cpuid.c: Added 7/1/edx CET_SSS: shadow stacks w/o page faults.
  * cpuid.c: Added several 7/2/edx bits.
  * cpuid.c: In 0xd/0/eax, corrected CET_U &amp; CET_S, which were IA32_XSS.
  * cpuid.c: In 0xd/0/eax, removed the IA32_XSS bits, which aren't
    relevant for XCR0.
  * cpuid.c: For 0xd/1/ecx, enumerate the IA32_XSS bits instead of a
    hex bitmask.
  * cpuid.c: For 0xd, added IA32_XSS PASID state (couple places).
  * cpuid.c: Renamed 0x1a: Native Model ID.
  * cpuid.c: Added synth &amp; uarch decoding for (0,6),(11,15) Raptor Lake
    from MSR_CPUID_table*.
  * cpuid.c: Added synth decoding for (0,6),(9,7),5 Pentium Gold G7400,
    based on instlatx64 sample.
  * cpuid.c: Added rudimentary synth decoding for future (0,6),(12,15)
    Emerald Rapids CPUs.
  * cpuid.c: Added 7/1/eax LASS: linear address space separation.
  * cpuid.c: Corrected 0x18/n/edx maximum number of addressible IDs, which
    should use minus-one notation.
  * cpuid.c: Certain leaves cannot be displayed correctly in isolation,
    i.e. without information about other leaves saved in the stash.  For
    example, the display for leaf 3 uses bits saved from leaf 1.  If the
  - l/--leaf option is used to restrict cpuid to reading only a single
    leaf, such leaves now are displayed as raw hex, rather than with
    incorrect information.  This is handled by passing a NULL stash to
    print_reg() and below, and by many new checks for a NULL stash.
  * cpuid.c: Updated cache associativity strings used in 0x80000006 and
    0x80000019 leaves to use value ranges, as in AMD docs.
  * cpuid.c: Fixed mistake in AMD L3 range reservation support: it's in
    0x80000020/0 register EBX, not ECX.
  * cpuid.c: Added 0x80000026/0/edx extended APIC ID.
  * cpuid.c: Added synth &amp; uarch decoding for (10,15),(1,1) Genoa, from
    AMD 57095 revision guide.
  * cpuid.man: Added AMD 57095 revision guides, and some older guides that
    I'd forgotten.</changelog>
  <changelog author="Egbert Eich &lt;eich@suse.com&gt;" date="1681473600">- Update to release 20230406:
  * Support APIC bit fields for the newest 4 topology layers:
    module, tile, die, die group.
  * Support leaf 0xb method for AMD/Hygon.
  * Added prelim Bergamo A1 stepping from sample.
  * Added AMX-COMPLEX instructions, UC-lock disable,
    non-contiguous 1s value support, event logging supported
    bitmap.
  * Update CPUID utility with new feature bits as documented in
    the AMD Processor Programming Reference for Family 19h and
    Model 11h: extended LVT offset fault cange, enhanced
    predictive store forwarding, FSRS, FSRC,
    FsGsKernelGsBaseNonSerializing, number of available UMC PMCs,
    bitmask representing active UMCs.
  * Added (synth) decoding for Sapphire Rapids D &amp; E0 steppings
  * Improved (synth) decoding for Scalable 3rd Gen Xeons to Ice
    Lake-SP, for Intel N-Series, for Raptor Lake-S/HX/P, for
    Raptor Lake-H/U/P.
  * Differentiate (synth) &amp; (uarch synth) for (0,6),(11,14)
    Alder Lake-N based on core type.
  * Differentiate Lakefield P-cores from Tremont E-cores.
  * Added (4th Gen) to the (synth) description of AMD EPYC Genoa.
  * Added (uarch synth) decoding for AMD Ryzen (Phoenix E0)
  * Added PkgType decoding for AMD Family 19h CPUs: Vermeer,
    Cezanne/Barcelo, Raphael, and Phoenix, based on their
    respective PPPRs.
  * Added Alder Lake Core names: i*-12000.
  * Decode Xen tsc mode.</changelog>
  <changelog author="Valentin Lefebvre &lt;valentin.lefebvre@suse.com&gt;" date="1687348800">- Update to release 20230614
  * Improved (synth) identification for Intel Xeon Scalable (3rd
    Gen) (Cooper Lake A0), Intel Xeon D-1700/2700 (Ice Lake-D),
    Intel Pentium Gold 8500 series, pure Atom x7000E, Atom C1100
    Arizona Beach.
  * Made the (simple synth) fields non-default. The (simple synth)
    fields still are available, but only with the -S/--simple
    option.
- Update to release 20230505
  * Fixed CPU counts for higher levels
    not dividing out counts from lower levels.
  * Differentiate Core i3-N300 N-Series from ordinary N-Series.
  * Added hypervisor+4/eax bit 21: use hypercalls for MMIO config
    space I/O, based on LX*.
  * Added (synth) decoding for Xeon W version of Sapphire Rapids,
    Meteor Lake-M B0.
  * Added (synth) &amp; (uarch synth) Emerald Rapids family: Raptor
    Cove, and Granite Rapids family: Redwood Cove.</changelog>
</package>
<package pkgid="291a6cf8bb1301787f5cecbd2ab6d4bb347fa35707f25b4d7b7ad42d682eaa8381c1ed86f060d3fc1ea543d0ea275163df722f9bc98de2401ac66e643fa9c30b" name="cpuid" arch="src">
  <version epoch="0" ver="20230614" rel="2.33"/>
  <changelog author="jengelh@inai.de" date="1433851200">- Update to new upstream release 20150606
  * Support for several leaf updates, including information on
  XSAVEC, XGETBV, and XSAVES/XRSTORS instructions. Decoding for
  more Haswell processors, Broadwell, Cherry Trail, and Avoton.
- %doc is already implicit for manpages</changelog>
  <changelog author="jengelh@inai.de" date="1446897600">- Update to new upstream release 20151017
  * Updated synth decoding for Broadwell processors.
  * Added 0xd leaf field.
  * Updated and expanded 0x14 leaf fields.
  * Added synth decoding for Intel Xeon E7 v2 (Ivy Bridge-EX).
  * Added synth decoding for Intel Core i5/i7 (Skylake).
  * Decode new leaf 2 cache descriptors: 6a, 6b, 6c, 6d.
  * added synth decoding for Knights Landing.
  * Added new &amp; missing decodings for: 4/ecx, 6/eax, 7/ebx, 7/ecx.
  * Renamed 0xf leaves to include "Monitoring".
  * Added 0x10 leaves for QoS Enforcement.
  * Added new leaf 2 cache meanings: 0x1d, 0x24, 0xa0, 0xc3.
  * Added missing i7 synth decoding for (0,6),(3,14).
  * Corrected Atom Z3000 model &amp; stepping which were bafflingly
  wrong: (0,6)(3,5),1 -&gt; (0,6)(3,7),8.
  * Corrected other Bay Trail stepping names for Celeron/Pentium
  N and J series.
  * Added synth decoding for Intel Xeon Phi (Knights Corner).
  * Added synth decoding for Intel Atom C2000 (Avoton).
  * Added synth decoding for Intel Xeon E5-x600 (Haswell-EP).
  * Added synth decoding for Intel Xeon E5-[48]800 (Haswell-EP).
  * Added synth decoding for Intel Core M (Broadwell-Y).
  * Added synth decoding for Intel Xeon D-1500 (Broadwell-DE).
  * Added synth decoding for Intel i7-5000 Extreme (Haswell R2).
  * Added synth decoding for Intel Atom Z8000 (Cherry Trail).
  * Added synth decoding for Intel Pentium/Celeron N3000</changelog>
  <changelog author="jengelh@inai.de" date="1472558400">- Update to new upstream release 20160814
  * cpuinfo2cpuid: Added a script that takes input from a
  /proc/cpuinfo file and converts it into suitable input to
  cpuid. The information that cpuid is capable of producing based
  on this very limited input information is slight, but
  apparently there is interest in getting the synthesized (synth)
  leaf from this.
  * Support SGX, MPX, BNDLDX/BNDSTX, RDPID, and IA32_XSS PT state.
  * Add information for Skylake, Broadwell, Broadwell-E and -EX
  processors, Atom C2000 (Avoton) with A0/A1 steppings, Atom
  Z3n00 (Bay Trail) stepping 1, Xeon D-1500 (Broadwell-DE) V2
  stepping, corrected Atom Z8000 (Cherry Trail), added Atom S1200
  (Centerton) and VIA Eden.</changelog>
  <changelog author="jengelh@inai.de" date="1479211200">- Update to new upstream release 20161114
  * cpuid.c: Added -l/--leaf and -s/--subleaf options to cause
  cpuid to dump just the specified leaf and subleaf. If
  - s/--subleaf is not specified, it is assumed to be 0. The
  intended purpose for this is to display raw dumps of
  not-yet-supported leaves.
  * cpuid.c: Added AVX512DQ, AVX512IFMA, AVX512BW, AVX512VL, and
  CLWB decoding to 7/ebx.
  * cpuid.c: Added AVX512VBMI to 7/ecx.
  * cpuid.c: Added print_f_0_edx to show L3 cache QoS monitoring
  support.
  * cpuid.c: Added total &amp; local bandwidth monitoring to 0xf/1/edx.
  * cpuid.c: Added 0x15/ecx nominal core crystal clock decoding.
  * cpuid.c: In print_17_0_ebx, corrected reversed scheme
  encodings.
  * cpuid.c: Added synth decoding for Xeon D-1500 (Broadwell-DE) Y0
  stepping.
  * cpuid.c: Added synth decoding comment about Braswell D1
  stepping, but its stepping number is not documented.
  * cpuid.c: Added synth decoding for (0,6),(8,14) Kaby Lake
  processors.
  * cpuid.c: Added synth decoding for Apollo Lake processors.
  * cpuid.c: Added vague synth decoding for (0,6),(9,14) Kaby Lake
  processors.
  * cpuid.c: Add AVX512_4VNNIW &amp; AVX512_4FMAPS flags.
  * cpuid.c: Add Knights Mill (KNM) CPUID.</changelog>
  <changelog author="jengelh@inai.de" date="1480680000">- Update to new upstream release 20161201
  * Fixed bugs in the subleaf walks for 0x8000001d (AMD cache
    information) and 0x40000003 (Xen hypervisor information) because
    the code for them was under wholly the wrong loops.</changelog>
  <changelog author="jengelh@inai.de" date="1485172800">- Update to new upstream release 20170122
  * Added synth decoding for Intel Knights Landing B0.
  * Added new synth decodings for Intel Kaby Lake.
  * Fixed synth decodings for AMD Steamroller and Jaguar.
  * Added synth decodings for AMD Puma and Excavator.
  * For (6,15),(0,2) Piledriver processors, detect FX series and
    report it as Vishera instead of Abu Dhabi/Seoul/Delhi.
  * Added general microarchitecure names for AMD (e.g.
    Piledriver) in addition to specific core names (e.g. Trinity)
    for later generation processors. If I have trouble
    remembering these, it seems likely other people do too.
  * Added synth decoding for Quark X1000.
  * Added Intel Atom Z2760 (Clover Trail).
  * Added extra synth decodings for some Ivy Bridge and Sandy
    Bridge processors.</changelog>
  <changelog author="josef.moellers@suse.com" date="1524225600">- Update to new upstream release 20180419
  * Added synth decoding for AMD Zen, Pentium Silver (Gemini
    Lake), Xeon Scalable (Bronze, Silver, Gold, Platinium)
    (Skylake), Core X-Series (Skylake-X), Bay Trail D0, Bay Trail
    A0, Xeon E7-4800/8800 (Broadwell-EX B0), Xeon D-1500N
    (Broadwell-DE A1), Bay Trail-I (E3800), Avoton C0 stepping.
  * Corrected synth decoding for Bay Trail-M C0 steppings.
  * Added new Intel 1b leaf from Intel Architecture.
  * Added various bit fields.</changelog>
  <changelog author="jengelh@inai.de" date="1526731200">- Update to new upstream release 20180519
  * Added 7/ecx bit 7: CET_SS and 7/edx bit 20: CET_IBT fields.
  * Added 7/ecx bit 16: 5-level paging.
  * Improved 14/0/ecx descriptions.
  * Added hypervisor leaf descriptions from Microsoft's
    Hypervisor Top Level Functional Specification (Released
    Version 5.0b).
  * Added CPUID features documented in PPR for AMD Family 17h
    Model 01h B1 (54945 Rev 1.14):
  * Added PCOMMIT to 7/ebx: PCOMMIT instruction (a deprecated
    instruction).
  * Added bits to 80000001/ecx (amd).
  * Added bits to 80000007/edx, 8000000a/edx, 8000001a/eax,
    8000001b/eax.
  * Added 80000007/ebx, 80000007/ecx, 80000008/ebx.
  * Added tentative 8000001f descriptions.</changelog>
  <changelog author="Josef M&#xF6;llers &lt;josef.moellers@suse.com&gt;" date="1579262400">- Upgrade to release 20200116
  many changes in Changelog: many new flags added.
  Also added support for Cyrix MediaGX, Matisse B0 stepping,
  Hygon CPUs.
  [cpuid-20200116.src.tar.gz]</changelog>
  <changelog author="Jan Engelhardt &lt;jengelh@inai.de&gt;" date="1583496000">- Update to release 20200211
  * Zhaoxin decoding
  * Name enhancements for models from AMD, VIA, Intel, NSC
  * Added SEV cpuid bit.</changelog>
  <changelog author="Andreas Stieger &lt;andreas.stieger@gmx.de&gt;" date="1588075200">- update to 20200427:
  * Add synth decoding for AMD Steppe Eagle/Crowned Eagle
    (Puma 2014 G-Series), based on instlatx64 sample
  * Add 7/0/edx SERIALIZE &amp; TSXLDTRK bit descriptions
  * Add 0xf/1/eax Counter width &amp; overflow flag
  * Add 0x10/3/ecx per-thread MBA controls flag
  * Add 0x8000001f fields
  * Add AMD 24594 &amp; 40332 docs
  * Correct field lengths in 14/0 and 14/1 subleafs so that
    columns line up
  * Add CC150 (Coffee Lake R0) synth decoding, based on
    instlatx64 example
  * Add Jasper Lake A0 stepping (from Coreboot*)
  * Update 1/ebx "cpu count" to modern terminology: "maximum
    addressible IDs for CPUs in pkg" to avoid user confusion
  * Update 4/eax CPU &amp; core count terminology in the same way</changelog>
  <changelog author="Josef M&#xF6;llers &lt;josef.moellers@suse.com&gt;" date="1602158400">- Update to 20201006:
  Added "Sapphire Rapids", "Golden Cove", "Rocket Lake", "Cato",
  14nm "Zen", "Tiger Lake-U B0", "Elkhart Lake B0", "Alder Lake",
  "Comet Lake", "Picasso A1", "Renoir A1", "Zhaoxin KaiXian KX-6000",
  as well as some additional decoding of supported features.
  [cpuid-20201006.src.tar.gz, jsc#sle-13189]</changelog>
  <changelog author="Andreas Stieger &lt;andreas.stieger@gmx.de&gt;" date="1636977600">- update to 20211114:
  * Many updated and added identified CPU models and variants
  * Updated hypervisor support</changelog>
  <changelog author="Andreas Stieger &lt;andreas.stieger@gmx.de&gt;" date="1645704000">- update to 20220224:
  * Support for AMD Rembrandt E1
  * Add hypervisor+4/eax (Xen) expanded destination id bit
  * Correction for Alder Lake, Rocket Lake decoding
  * Multiple detection and decodings updated</changelog>
  <changelog author="Jan Engelhardt &lt;jengelh@inai.de&gt;" date="1660392000">- Update to release 20220812
  * Corrected (synth) decoding for (0,6),(8,6) Intel Snow
    Ridge/Parker Ridge.
  * Added 8000000a/edx X2AVIC flag
  * Generalized (0,6),(8,14),9,YP stepping case to include
    Pentium 4425Y, from instlatx64 sample.
  * Added support for hypervisor+3/ecx (Microsoft) flags.</changelog>
  <changelog author="Valentin Lefebvre &lt;valentin.lefebvre@suse.com&gt;" date="1665662400">- Update to release 20221003
  * Added synth decoding for AMD Ryzen (Phoenix E0, Storm Peak A1)
  * Added synth &amp; uarch synth decoding for
  * (0,6),(11,5) Intel Meteor Lake
  * (0,6),(11,6) Intel Grand Ridge (Crestmont)
  * (0,6),(11,14) Intel Granite Rapids
  * Renamed 7/0/eax enh hardware feedback to just "Thread
    Director".
  * Added 7/1/eax instructions.
  * Added 0x12/0/eax SGX ENCLU EDECCSA flag.
  * Added 0x23 Architecture Performance Monitoring Extended leaf
    decoding.
  * Corrected AVX512IFMA description: integer FMA, not just FMA.
- Release 20220927
  * Added synth decoding for (10,15),(6,1) Raphael
  * Fixed title for AMD 0x8000001a leaf: Performance Optimization
    identifiers.</changelog>
  <changelog author="Valentin Lefebvre &lt;valentin.lefebvre@suse.com&gt;" date="1670241600">- Update to release 20221201
  * Clarified synth decoding for Intel Xeon D-1700.
  * Added uarch &amp; synth decoding for AMD 4800S Desktop Kit, based on
    instlatx64 sample.
  * Added uarch decoding for AMD Genoa A1, based on instlatx64 sample
  * Added uarch decoding for (0,6),(12,15) Emerald Rapids, from LX*.
  * Added synth &amp; uarch decoding for (10,15),(10,1) Bergamo.
  * Added 0x8000000a/edx bits: ROGPT, VNMI, IBS virtualization.
  * Added 0x8000001b/eax bit: IBS L3 miss filtering support.
  * Added 0x8000001f/eax bits: RMPQUERY instruction support,
    VMPL supervisor shadow stack support, VMGEXIT parameter support,
    virtual TOM MSR support, IBS virtual support for SEV-ES guests,
    SMT protection support, SVSM communication page MSR support,
    VIRT_RMPUPDATE &amp; VIRT_PSMASH MSR support.
  * Added 0x80000020/0/ecx bit: L3 range reservation support.
  * Added 0x80000021/eax bits: automatic IBRS,
    CPUID disable for non-privileged.
  * Added 0x80000022/eax bit: AMD LBR &amp; PMC freezing.
  * Added 0x80000022/ebx field: number of LBR stack entries.
  * Added 0x80000023 leaf: Multi-Key Encrypted Memory Capabilities.
  * Added 0x80000026 leaf: AMD Extended CPU Topology.
  * cpuid.c: use lseek64 and cpuset_setaffinity, Added 0x80000022/eax
    AMD LBR V2 flag, from LX*.</changelog>
  <changelog author="Dirk M&#xFC;ller &lt;dmueller@suse.com&gt;" date="1674907200">- updated to 20230120:
  * Intel's 13th Generation Core datasheet provides stepping names as
    well as numbers!  So:
  * cpuid.c: Added synth decoding for (0,6),(11,7) Raptor Lake B0 stepping.
  * cpuid.c: Added synth decoding for (0,6),(11,15) Raptor Lake C0
    steppings, and clarified case for unknown stepping.
  * cpuid.man: Added 743844: 13th Generation Core datasheet.
  * cpuid.c: Fixed (0,6)(12,15) synth typo: Emearld Rapids.
  * cpuid.c: Added 6/eax IA32_HW_FEEDBACK_THREAD_CONFIG bit 25.
  * cpuid.c: Added 7/0/edx SGX-KEYS: SGX attestation services.
  * cpuid.c: Clarified 7/0/edx IA32_MCU_OPT_CTRL SRBDS mitigation MSR.
  * cpuid.c: Clarified 7/0/edx IA32_TSX_FORCE_ABORT MSR.
  * cpuid.c: Added 7/1/edx CET_SSS: shadow stacks w/o page faults.
  * cpuid.c: Added several 7/2/edx bits.
  * cpuid.c: In 0xd/0/eax, corrected CET_U &amp; CET_S, which were IA32_XSS.
  * cpuid.c: In 0xd/0/eax, removed the IA32_XSS bits, which aren't
    relevant for XCR0.
  * cpuid.c: For 0xd/1/ecx, enumerate the IA32_XSS bits instead of a
    hex bitmask.
  * cpuid.c: For 0xd, added IA32_XSS PASID state (couple places).
  * cpuid.c: Renamed 0x1a: Native Model ID.
  * cpuid.c: Added synth &amp; uarch decoding for (0,6),(11,15) Raptor Lake
    from MSR_CPUID_table*.
  * cpuid.c: Added synth decoding for (0,6),(9,7),5 Pentium Gold G7400,
    based on instlatx64 sample.
  * cpuid.c: Added rudimentary synth decoding for future (0,6),(12,15)
    Emerald Rapids CPUs.
  * cpuid.c: Added 7/1/eax LASS: linear address space separation.
  * cpuid.c: Corrected 0x18/n/edx maximum number of addressible IDs, which
    should use minus-one notation.
  * cpuid.c: Certain leaves cannot be displayed correctly in isolation,
    i.e. without information about other leaves saved in the stash.  For
    example, the display for leaf 3 uses bits saved from leaf 1.  If the
  - l/--leaf option is used to restrict cpuid to reading only a single
    leaf, such leaves now are displayed as raw hex, rather than with
    incorrect information.  This is handled by passing a NULL stash to
    print_reg() and below, and by many new checks for a NULL stash.
  * cpuid.c: Updated cache associativity strings used in 0x80000006 and
    0x80000019 leaves to use value ranges, as in AMD docs.
  * cpuid.c: Fixed mistake in AMD L3 range reservation support: it's in
    0x80000020/0 register EBX, not ECX.
  * cpuid.c: Added 0x80000026/0/edx extended APIC ID.
  * cpuid.c: Added synth &amp; uarch decoding for (10,15),(1,1) Genoa, from
    AMD 57095 revision guide.
  * cpuid.man: Added AMD 57095 revision guides, and some older guides that
    I'd forgotten.</changelog>
  <changelog author="Egbert Eich &lt;eich@suse.com&gt;" date="1681473600">- Update to release 20230406:
  * Support APIC bit fields for the newest 4 topology layers:
    module, tile, die, die group.
  * Support leaf 0xb method for AMD/Hygon.
  * Added prelim Bergamo A1 stepping from sample.
  * Added AMX-COMPLEX instructions, UC-lock disable,
    non-contiguous 1s value support, event logging supported
    bitmap.
  * Update CPUID utility with new feature bits as documented in
    the AMD Processor Programming Reference for Family 19h and
    Model 11h: extended LVT offset fault cange, enhanced
    predictive store forwarding, FSRS, FSRC,
    FsGsKernelGsBaseNonSerializing, number of available UMC PMCs,
    bitmask representing active UMCs.
  * Added (synth) decoding for Sapphire Rapids D &amp; E0 steppings
  * Improved (synth) decoding for Scalable 3rd Gen Xeons to Ice
    Lake-SP, for Intel N-Series, for Raptor Lake-S/HX/P, for
    Raptor Lake-H/U/P.
  * Differentiate (synth) &amp; (uarch synth) for (0,6),(11,14)
    Alder Lake-N based on core type.
  * Differentiate Lakefield P-cores from Tremont E-cores.
  * Added (4th Gen) to the (synth) description of AMD EPYC Genoa.
  * Added (uarch synth) decoding for AMD Ryzen (Phoenix E0)
  * Added PkgType decoding for AMD Family 19h CPUs: Vermeer,
    Cezanne/Barcelo, Raphael, and Phoenix, based on their
    respective PPPRs.
  * Added Alder Lake Core names: i*-12000.
  * Decode Xen tsc mode.</changelog>
  <changelog author="Valentin Lefebvre &lt;valentin.lefebvre@suse.com&gt;" date="1687348800">- Update to release 20230614
  * Improved (synth) identification for Intel Xeon Scalable (3rd
    Gen) (Cooper Lake A0), Intel Xeon D-1700/2700 (Ice Lake-D),
    Intel Pentium Gold 8500 series, pure Atom x7000E, Atom C1100
    Arizona Beach.
  * Made the (simple synth) fields non-default. The (simple synth)
    fields still are available, but only with the -S/--simple
    option.
- Update to release 20230505
  * Fixed CPU counts for higher levels
    not dividing out counts from lower levels.
  * Differentiate Core i3-N300 N-Series from ordinary N-Series.
  * Added hypervisor+4/eax bit 21: use hypercalls for MMIO config
    space I/O, based on LX*.
  * Added (synth) decoding for Xeon W version of Sapphire Rapids,
    Meteor Lake-M B0.
  * Added (synth) &amp; (uarch synth) Emerald Rapids family: Raptor
    Cove, and Granite Rapids family: Redwood Cove.</changelog>
</package>
<package pkgid="94ced5ef0a3aaacaead84ade219de69de7e42fdfbd69e11b3781561d1781d11e662bdaa9a7f665073205c48f63cc466509239e9d1cc0e055b82e7d081bf3c1da" name="cpuid" arch="x86_64">
  <version epoch="0" ver="20230614" rel="2.33"/>
  <changelog author="Andreas Stieger &lt;andreas.stieger@gmx.de&gt;" date="1588075200">- update to 20200427:
  * Add synth decoding for AMD Steppe Eagle/Crowned Eagle
    (Puma 2014 G-Series), based on instlatx64 sample
  * Add 7/0/edx SERIALIZE &amp; TSXLDTRK bit descriptions
  * Add 0xf/1/eax Counter width &amp; overflow flag
  * Add 0x10/3/ecx per-thread MBA controls flag
  * Add 0x8000001f fields
  * Add AMD 24594 &amp; 40332 docs
  * Correct field lengths in 14/0 and 14/1 subleafs so that
    columns line up
  * Add CC150 (Coffee Lake R0) synth decoding, based on
    instlatx64 example
  * Add Jasper Lake A0 stepping (from Coreboot*)
  * Update 1/ebx "cpu count" to modern terminology: "maximum
    addressible IDs for CPUs in pkg" to avoid user confusion
  * Update 4/eax CPU &amp; core count terminology in the same way</changelog>
  <changelog author="Josef M&#xF6;llers &lt;josef.moellers@suse.com&gt;" date="1602158400">- Update to 20201006:
  Added "Sapphire Rapids", "Golden Cove", "Rocket Lake", "Cato",
  14nm "Zen", "Tiger Lake-U B0", "Elkhart Lake B0", "Alder Lake",
  "Comet Lake", "Picasso A1", "Renoir A1", "Zhaoxin KaiXian KX-6000",
  as well as some additional decoding of supported features.
  [cpuid-20201006.src.tar.gz, jsc#sle-13189]</changelog>
  <changelog author="Andreas Stieger &lt;andreas.stieger@gmx.de&gt;" date="1636977600">- update to 20211114:
  * Many updated and added identified CPU models and variants
  * Updated hypervisor support</changelog>
  <changelog author="Andreas Stieger &lt;andreas.stieger@gmx.de&gt;" date="1645704000">- update to 20220224:
  * Support for AMD Rembrandt E1
  * Add hypervisor+4/eax (Xen) expanded destination id bit
  * Correction for Alder Lake, Rocket Lake decoding
  * Multiple detection and decodings updated</changelog>
  <changelog author="Jan Engelhardt &lt;jengelh@inai.de&gt;" date="1660392000">- Update to release 20220812
  * Corrected (synth) decoding for (0,6),(8,6) Intel Snow
    Ridge/Parker Ridge.
  * Added 8000000a/edx X2AVIC flag
  * Generalized (0,6),(8,14),9,YP stepping case to include
    Pentium 4425Y, from instlatx64 sample.
  * Added support for hypervisor+3/ecx (Microsoft) flags.</changelog>
  <changelog author="Valentin Lefebvre &lt;valentin.lefebvre@suse.com&gt;" date="1665662400">- Update to release 20221003
  * Added synth decoding for AMD Ryzen (Phoenix E0, Storm Peak A1)
  * Added synth &amp; uarch synth decoding for
  * (0,6),(11,5) Intel Meteor Lake
  * (0,6),(11,6) Intel Grand Ridge (Crestmont)
  * (0,6),(11,14) Intel Granite Rapids
  * Renamed 7/0/eax enh hardware feedback to just "Thread
    Director".
  * Added 7/1/eax instructions.
  * Added 0x12/0/eax SGX ENCLU EDECCSA flag.
  * Added 0x23 Architecture Performance Monitoring Extended leaf
    decoding.
  * Corrected AVX512IFMA description: integer FMA, not just FMA.
- Release 20220927
  * Added synth decoding for (10,15),(6,1) Raphael
  * Fixed title for AMD 0x8000001a leaf: Performance Optimization
    identifiers.</changelog>
  <changelog author="Valentin Lefebvre &lt;valentin.lefebvre@suse.com&gt;" date="1670241600">- Update to release 20221201
  * Clarified synth decoding for Intel Xeon D-1700.
  * Added uarch &amp; synth decoding for AMD 4800S Desktop Kit, based on
    instlatx64 sample.
  * Added uarch decoding for AMD Genoa A1, based on instlatx64 sample
  * Added uarch decoding for (0,6),(12,15) Emerald Rapids, from LX*.
  * Added synth &amp; uarch decoding for (10,15),(10,1) Bergamo.
  * Added 0x8000000a/edx bits: ROGPT, VNMI, IBS virtualization.
  * Added 0x8000001b/eax bit: IBS L3 miss filtering support.
  * Added 0x8000001f/eax bits: RMPQUERY instruction support,
    VMPL supervisor shadow stack support, VMGEXIT parameter support,
    virtual TOM MSR support, IBS virtual support for SEV-ES guests,
    SMT protection support, SVSM communication page MSR support,
    VIRT_RMPUPDATE &amp; VIRT_PSMASH MSR support.
  * Added 0x80000020/0/ecx bit: L3 range reservation support.
  * Added 0x80000021/eax bits: automatic IBRS,
    CPUID disable for non-privileged.
  * Added 0x80000022/eax bit: AMD LBR &amp; PMC freezing.
  * Added 0x80000022/ebx field: number of LBR stack entries.
  * Added 0x80000023 leaf: Multi-Key Encrypted Memory Capabilities.
  * Added 0x80000026 leaf: AMD Extended CPU Topology.
  * cpuid.c: use lseek64 and cpuset_setaffinity, Added 0x80000022/eax
    AMD LBR V2 flag, from LX*.</changelog>
  <changelog author="Dirk M&#xFC;ller &lt;dmueller@suse.com&gt;" date="1674907200">- updated to 20230120:
  * Intel's 13th Generation Core datasheet provides stepping names as
    well as numbers!  So:
  * cpuid.c: Added synth decoding for (0,6),(11,7) Raptor Lake B0 stepping.
  * cpuid.c: Added synth decoding for (0,6),(11,15) Raptor Lake C0
    steppings, and clarified case for unknown stepping.
  * cpuid.man: Added 743844: 13th Generation Core datasheet.
  * cpuid.c: Fixed (0,6)(12,15) synth typo: Emearld Rapids.
  * cpuid.c: Added 6/eax IA32_HW_FEEDBACK_THREAD_CONFIG bit 25.
  * cpuid.c: Added 7/0/edx SGX-KEYS: SGX attestation services.
  * cpuid.c: Clarified 7/0/edx IA32_MCU_OPT_CTRL SRBDS mitigation MSR.
  * cpuid.c: Clarified 7/0/edx IA32_TSX_FORCE_ABORT MSR.
  * cpuid.c: Added 7/1/edx CET_SSS: shadow stacks w/o page faults.
  * cpuid.c: Added several 7/2/edx bits.
  * cpuid.c: In 0xd/0/eax, corrected CET_U &amp; CET_S, which were IA32_XSS.
  * cpuid.c: In 0xd/0/eax, removed the IA32_XSS bits, which aren't
    relevant for XCR0.
  * cpuid.c: For 0xd/1/ecx, enumerate the IA32_XSS bits instead of a
    hex bitmask.
  * cpuid.c: For 0xd, added IA32_XSS PASID state (couple places).
  * cpuid.c: Renamed 0x1a: Native Model ID.
  * cpuid.c: Added synth &amp; uarch decoding for (0,6),(11,15) Raptor Lake
    from MSR_CPUID_table*.
  * cpuid.c: Added synth decoding for (0,6),(9,7),5 Pentium Gold G7400,
    based on instlatx64 sample.
  * cpuid.c: Added rudimentary synth decoding for future (0,6),(12,15)
    Emerald Rapids CPUs.
  * cpuid.c: Added 7/1/eax LASS: linear address space separation.
  * cpuid.c: Corrected 0x18/n/edx maximum number of addressible IDs, which
    should use minus-one notation.
  * cpuid.c: Certain leaves cannot be displayed correctly in isolation,
    i.e. without information about other leaves saved in the stash.  For
    example, the display for leaf 3 uses bits saved from leaf 1.  If the
  - l/--leaf option is used to restrict cpuid to reading only a single
    leaf, such leaves now are displayed as raw hex, rather than with
    incorrect information.  This is handled by passing a NULL stash to
    print_reg() and below, and by many new checks for a NULL stash.
  * cpuid.c: Updated cache associativity strings used in 0x80000006 and
    0x80000019 leaves to use value ranges, as in AMD docs.
  * cpuid.c: Fixed mistake in AMD L3 range reservation support: it's in
    0x80000020/0 register EBX, not ECX.
  * cpuid.c: Added 0x80000026/0/edx extended APIC ID.
  * cpuid.c: Added synth &amp; uarch decoding for (10,15),(1,1) Genoa, from
    AMD 57095 revision guide.
  * cpuid.man: Added AMD 57095 revision guides, and some older guides that
    I'd forgotten.</changelog>
  <changelog author="Egbert Eich &lt;eich@suse.com&gt;" date="1681473600">- Update to release 20230406:
  * Support APIC bit fields for the newest 4 topology layers:
    module, tile, die, die group.
  * Support leaf 0xb method for AMD/Hygon.
  * Added prelim Bergamo A1 stepping from sample.
  * Added AMX-COMPLEX instructions, UC-lock disable,
    non-contiguous 1s value support, event logging supported
    bitmap.
  * Update CPUID utility with new feature bits as documented in
    the AMD Processor Programming Reference for Family 19h and
    Model 11h: extended LVT offset fault cange, enhanced
    predictive store forwarding, FSRS, FSRC,
    FsGsKernelGsBaseNonSerializing, number of available UMC PMCs,
    bitmask representing active UMCs.
  * Added (synth) decoding for Sapphire Rapids D &amp; E0 steppings
  * Improved (synth) decoding for Scalable 3rd Gen Xeons to Ice
    Lake-SP, for Intel N-Series, for Raptor Lake-S/HX/P, for
    Raptor Lake-H/U/P.
  * Differentiate (synth) &amp; (uarch synth) for (0,6),(11,14)
    Alder Lake-N based on core type.
  * Differentiate Lakefield P-cores from Tremont E-cores.
  * Added (4th Gen) to the (synth) description of AMD EPYC Genoa.
  * Added (uarch synth) decoding for AMD Ryzen (Phoenix E0)
  * Added PkgType decoding for AMD Family 19h CPUs: Vermeer,
    Cezanne/Barcelo, Raphael, and Phoenix, based on their
    respective PPPRs.
  * Added Alder Lake Core names: i*-12000.
  * Decode Xen tsc mode.</changelog>
  <changelog author="Valentin Lefebvre &lt;valentin.lefebvre@suse.com&gt;" date="1687348800">- Update to release 20230614
  * Improved (synth) identification for Intel Xeon Scalable (3rd
    Gen) (Cooper Lake A0), Intel Xeon D-1700/2700 (Ice Lake-D),
    Intel Pentium Gold 8500 series, pure Atom x7000E, Atom C1100
    Arizona Beach.
  * Made the (simple synth) fields non-default. The (simple synth)
    fields still are available, but only with the -S/--simple
    option.
- Update to release 20230505
  * Fixed CPU counts for higher levels
    not dividing out counts from lower levels.
  * Differentiate Core i3-N300 N-Series from ordinary N-Series.
  * Added hypervisor+4/eax bit 21: use hypercalls for MMIO config
    space I/O, based on LX*.
  * Added (synth) decoding for Xeon W version of Sapphire Rapids,
    Meteor Lake-M B0.
  * Added (synth) &amp; (uarch synth) Emerald Rapids family: Raptor
    Cove, and Granite Rapids family: Redwood Cove.</changelog>
</package>
<package pkgid="b284b34522602f7510ccef64f3e000659e4e1635df1c0fc50de0a5e835688fd5b4c07a2ff8d57778a87dda350539d7cb834b501d6e54dc4b9cf6597c2f624163" name="cpuid-debuginfo" arch="i586">
  <version epoch="0" ver="20230614" rel="2.33"/>
  <changelog author="Andreas Stieger &lt;andreas.stieger@gmx.de&gt;" date="1588075200">- update to 20200427:
  * Add synth decoding for AMD Steppe Eagle/Crowned Eagle
    (Puma 2014 G-Series), based on instlatx64 sample
  * Add 7/0/edx SERIALIZE &amp; TSXLDTRK bit descriptions
  * Add 0xf/1/eax Counter width &amp; overflow flag
  * Add 0x10/3/ecx per-thread MBA controls flag
  * Add 0x8000001f fields
  * Add AMD 24594 &amp; 40332 docs
  * Correct field lengths in 14/0 and 14/1 subleafs so that
    columns line up
  * Add CC150 (Coffee Lake R0) synth decoding, based on
    instlatx64 example
  * Add Jasper Lake A0 stepping (from Coreboot*)
  * Update 1/ebx "cpu count" to modern terminology: "maximum
    addressible IDs for CPUs in pkg" to avoid user confusion
  * Update 4/eax CPU &amp; core count terminology in the same way</changelog>
  <changelog author="Josef M&#xF6;llers &lt;josef.moellers@suse.com&gt;" date="1602158400">- Update to 20201006:
  Added "Sapphire Rapids", "Golden Cove", "Rocket Lake", "Cato",
  14nm "Zen", "Tiger Lake-U B0", "Elkhart Lake B0", "Alder Lake",
  "Comet Lake", "Picasso A1", "Renoir A1", "Zhaoxin KaiXian KX-6000",
  as well as some additional decoding of supported features.
  [cpuid-20201006.src.tar.gz, jsc#sle-13189]</changelog>
  <changelog author="Andreas Stieger &lt;andreas.stieger@gmx.de&gt;" date="1636977600">- update to 20211114:
  * Many updated and added identified CPU models and variants
  * Updated hypervisor support</changelog>
  <changelog author="Andreas Stieger &lt;andreas.stieger@gmx.de&gt;" date="1645704000">- update to 20220224:
  * Support for AMD Rembrandt E1
  * Add hypervisor+4/eax (Xen) expanded destination id bit
  * Correction for Alder Lake, Rocket Lake decoding
  * Multiple detection and decodings updated</changelog>
  <changelog author="Jan Engelhardt &lt;jengelh@inai.de&gt;" date="1660392000">- Update to release 20220812
  * Corrected (synth) decoding for (0,6),(8,6) Intel Snow
    Ridge/Parker Ridge.
  * Added 8000000a/edx X2AVIC flag
  * Generalized (0,6),(8,14),9,YP stepping case to include
    Pentium 4425Y, from instlatx64 sample.
  * Added support for hypervisor+3/ecx (Microsoft) flags.</changelog>
  <changelog author="Valentin Lefebvre &lt;valentin.lefebvre@suse.com&gt;" date="1665662400">- Update to release 20221003
  * Added synth decoding for AMD Ryzen (Phoenix E0, Storm Peak A1)
  * Added synth &amp; uarch synth decoding for
  * (0,6),(11,5) Intel Meteor Lake
  * (0,6),(11,6) Intel Grand Ridge (Crestmont)
  * (0,6),(11,14) Intel Granite Rapids
  * Renamed 7/0/eax enh hardware feedback to just "Thread
    Director".
  * Added 7/1/eax instructions.
  * Added 0x12/0/eax SGX ENCLU EDECCSA flag.
  * Added 0x23 Architecture Performance Monitoring Extended leaf
    decoding.
  * Corrected AVX512IFMA description: integer FMA, not just FMA.
- Release 20220927
  * Added synth decoding for (10,15),(6,1) Raphael
  * Fixed title for AMD 0x8000001a leaf: Performance Optimization
    identifiers.</changelog>
  <changelog author="Valentin Lefebvre &lt;valentin.lefebvre@suse.com&gt;" date="1670241600">- Update to release 20221201
  * Clarified synth decoding for Intel Xeon D-1700.
  * Added uarch &amp; synth decoding for AMD 4800S Desktop Kit, based on
    instlatx64 sample.
  * Added uarch decoding for AMD Genoa A1, based on instlatx64 sample
  * Added uarch decoding for (0,6),(12,15) Emerald Rapids, from LX*.
  * Added synth &amp; uarch decoding for (10,15),(10,1) Bergamo.
  * Added 0x8000000a/edx bits: ROGPT, VNMI, IBS virtualization.
  * Added 0x8000001b/eax bit: IBS L3 miss filtering support.
  * Added 0x8000001f/eax bits: RMPQUERY instruction support,
    VMPL supervisor shadow stack support, VMGEXIT parameter support,
    virtual TOM MSR support, IBS virtual support for SEV-ES guests,
    SMT protection support, SVSM communication page MSR support,
    VIRT_RMPUPDATE &amp; VIRT_PSMASH MSR support.
  * Added 0x80000020/0/ecx bit: L3 range reservation support.
  * Added 0x80000021/eax bits: automatic IBRS,
    CPUID disable for non-privileged.
  * Added 0x80000022/eax bit: AMD LBR &amp; PMC freezing.
  * Added 0x80000022/ebx field: number of LBR stack entries.
  * Added 0x80000023 leaf: Multi-Key Encrypted Memory Capabilities.
  * Added 0x80000026 leaf: AMD Extended CPU Topology.
  * cpuid.c: use lseek64 and cpuset_setaffinity, Added 0x80000022/eax
    AMD LBR V2 flag, from LX*.</changelog>
  <changelog author="Dirk M&#xFC;ller &lt;dmueller@suse.com&gt;" date="1674907200">- updated to 20230120:
  * Intel's 13th Generation Core datasheet provides stepping names as
    well as numbers!  So:
  * cpuid.c: Added synth decoding for (0,6),(11,7) Raptor Lake B0 stepping.
  * cpuid.c: Added synth decoding for (0,6),(11,15) Raptor Lake C0
    steppings, and clarified case for unknown stepping.
  * cpuid.man: Added 743844: 13th Generation Core datasheet.
  * cpuid.c: Fixed (0,6)(12,15) synth typo: Emearld Rapids.
  * cpuid.c: Added 6/eax IA32_HW_FEEDBACK_THREAD_CONFIG bit 25.
  * cpuid.c: Added 7/0/edx SGX-KEYS: SGX attestation services.
  * cpuid.c: Clarified 7/0/edx IA32_MCU_OPT_CTRL SRBDS mitigation MSR.
  * cpuid.c: Clarified 7/0/edx IA32_TSX_FORCE_ABORT MSR.
  * cpuid.c: Added 7/1/edx CET_SSS: shadow stacks w/o page faults.
  * cpuid.c: Added several 7/2/edx bits.
  * cpuid.c: In 0xd/0/eax, corrected CET_U &amp; CET_S, which were IA32_XSS.
  * cpuid.c: In 0xd/0/eax, removed the IA32_XSS bits, which aren't
    relevant for XCR0.
  * cpuid.c: For 0xd/1/ecx, enumerate the IA32_XSS bits instead of a
    hex bitmask.
  * cpuid.c: For 0xd, added IA32_XSS PASID state (couple places).
  * cpuid.c: Renamed 0x1a: Native Model ID.
  * cpuid.c: Added synth &amp; uarch decoding for (0,6),(11,15) Raptor Lake
    from MSR_CPUID_table*.
  * cpuid.c: Added synth decoding for (0,6),(9,7),5 Pentium Gold G7400,
    based on instlatx64 sample.
  * cpuid.c: Added rudimentary synth decoding for future (0,6),(12,15)
    Emerald Rapids CPUs.
  * cpuid.c: Added 7/1/eax LASS: linear address space separation.
  * cpuid.c: Corrected 0x18/n/edx maximum number of addressible IDs, which
    should use minus-one notation.
  * cpuid.c: Certain leaves cannot be displayed correctly in isolation,
    i.e. without information about other leaves saved in the stash.  For
    example, the display for leaf 3 uses bits saved from leaf 1.  If the
  - l/--leaf option is used to restrict cpuid to reading only a single
    leaf, such leaves now are displayed as raw hex, rather than with
    incorrect information.  This is handled by passing a NULL stash to
    print_reg() and below, and by many new checks for a NULL stash.
  * cpuid.c: Updated cache associativity strings used in 0x80000006 and
    0x80000019 leaves to use value ranges, as in AMD docs.
  * cpuid.c: Fixed mistake in AMD L3 range reservation support: it's in
    0x80000020/0 register EBX, not ECX.
  * cpuid.c: Added 0x80000026/0/edx extended APIC ID.
  * cpuid.c: Added synth &amp; uarch decoding for (10,15),(1,1) Genoa, from
    AMD 57095 revision guide.
  * cpuid.man: Added AMD 57095 revision guides, and some older guides that
    I'd forgotten.</changelog>
  <changelog author="Egbert Eich &lt;eich@suse.com&gt;" date="1681473600">- Update to release 20230406:
  * Support APIC bit fields for the newest 4 topology layers:
    module, tile, die, die group.
  * Support leaf 0xb method for AMD/Hygon.
  * Added prelim Bergamo A1 stepping from sample.
  * Added AMX-COMPLEX instructions, UC-lock disable,
    non-contiguous 1s value support, event logging supported
    bitmap.
  * Update CPUID utility with new feature bits as documented in
    the AMD Processor Programming Reference for Family 19h and
    Model 11h: extended LVT offset fault cange, enhanced
    predictive store forwarding, FSRS, FSRC,
    FsGsKernelGsBaseNonSerializing, number of available UMC PMCs,
    bitmask representing active UMCs.
  * Added (synth) decoding for Sapphire Rapids D &amp; E0 steppings
  * Improved (synth) decoding for Scalable 3rd Gen Xeons to Ice
    Lake-SP, for Intel N-Series, for Raptor Lake-S/HX/P, for
    Raptor Lake-H/U/P.
  * Differentiate (synth) &amp; (uarch synth) for (0,6),(11,14)
    Alder Lake-N based on core type.
  * Differentiate Lakefield P-cores from Tremont E-cores.
  * Added (4th Gen) to the (synth) description of AMD EPYC Genoa.
  * Added (uarch synth) decoding for AMD Ryzen (Phoenix E0)
  * Added PkgType decoding for AMD Family 19h CPUs: Vermeer,
    Cezanne/Barcelo, Raphael, and Phoenix, based on their
    respective PPPRs.
  * Added Alder Lake Core names: i*-12000.
  * Decode Xen tsc mode.</changelog>
  <changelog author="Valentin Lefebvre &lt;valentin.lefebvre@suse.com&gt;" date="1687348800">- Update to release 20230614
  * Improved (synth) identification for Intel Xeon Scalable (3rd
    Gen) (Cooper Lake A0), Intel Xeon D-1700/2700 (Ice Lake-D),
    Intel Pentium Gold 8500 series, pure Atom x7000E, Atom C1100
    Arizona Beach.
  * Made the (simple synth) fields non-default. The (simple synth)
    fields still are available, but only with the -S/--simple
    option.
- Update to release 20230505
  * Fixed CPU counts for higher levels
    not dividing out counts from lower levels.
  * Differentiate Core i3-N300 N-Series from ordinary N-Series.
  * Added hypervisor+4/eax bit 21: use hypercalls for MMIO config
    space I/O, based on LX*.
  * Added (synth) decoding for Xeon W version of Sapphire Rapids,
    Meteor Lake-M B0.
  * Added (synth) &amp; (uarch synth) Emerald Rapids family: Raptor
    Cove, and Granite Rapids family: Redwood Cove.</changelog>
</package>
<package pkgid="9b575c5bff6c0559fbe1d333e1ad55159b98482716b048dabea36c314d375a626684becf168c3502816ec52adcc6d1fb725e9f8137972e593b594bf698c200f3" name="cpuid-debuginfo" arch="x86_64">
  <version epoch="0" ver="20230614" rel="2.33"/>
  <changelog author="Andreas Stieger &lt;andreas.stieger@gmx.de&gt;" date="1588075200">- update to 20200427:
  * Add synth decoding for AMD Steppe Eagle/Crowned Eagle
    (Puma 2014 G-Series), based on instlatx64 sample
  * Add 7/0/edx SERIALIZE &amp; TSXLDTRK bit descriptions
  * Add 0xf/1/eax Counter width &amp; overflow flag
  * Add 0x10/3/ecx per-thread MBA controls flag
  * Add 0x8000001f fields
  * Add AMD 24594 &amp; 40332 docs
  * Correct field lengths in 14/0 and 14/1 subleafs so that
    columns line up
  * Add CC150 (Coffee Lake R0) synth decoding, based on
    instlatx64 example
  * Add Jasper Lake A0 stepping (from Coreboot*)
  * Update 1/ebx "cpu count" to modern terminology: "maximum
    addressible IDs for CPUs in pkg" to avoid user confusion
  * Update 4/eax CPU &amp; core count terminology in the same way</changelog>
  <changelog author="Josef M&#xF6;llers &lt;josef.moellers@suse.com&gt;" date="1602158400">- Update to 20201006:
  Added "Sapphire Rapids", "Golden Cove", "Rocket Lake", "Cato",
  14nm "Zen", "Tiger Lake-U B0", "Elkhart Lake B0", "Alder Lake",
  "Comet Lake", "Picasso A1", "Renoir A1", "Zhaoxin KaiXian KX-6000",
  as well as some additional decoding of supported features.
  [cpuid-20201006.src.tar.gz, jsc#sle-13189]</changelog>
  <changelog author="Andreas Stieger &lt;andreas.stieger@gmx.de&gt;" date="1636977600">- update to 20211114:
  * Many updated and added identified CPU models and variants
  * Updated hypervisor support</changelog>
  <changelog author="Andreas Stieger &lt;andreas.stieger@gmx.de&gt;" date="1645704000">- update to 20220224:
  * Support for AMD Rembrandt E1
  * Add hypervisor+4/eax (Xen) expanded destination id bit
  * Correction for Alder Lake, Rocket Lake decoding
  * Multiple detection and decodings updated</changelog>
  <changelog author="Jan Engelhardt &lt;jengelh@inai.de&gt;" date="1660392000">- Update to release 20220812
  * Corrected (synth) decoding for (0,6),(8,6) Intel Snow
    Ridge/Parker Ridge.
  * Added 8000000a/edx X2AVIC flag
  * Generalized (0,6),(8,14),9,YP stepping case to include
    Pentium 4425Y, from instlatx64 sample.
  * Added support for hypervisor+3/ecx (Microsoft) flags.</changelog>
  <changelog author="Valentin Lefebvre &lt;valentin.lefebvre@suse.com&gt;" date="1665662400">- Update to release 20221003
  * Added synth decoding for AMD Ryzen (Phoenix E0, Storm Peak A1)
  * Added synth &amp; uarch synth decoding for
  * (0,6),(11,5) Intel Meteor Lake
  * (0,6),(11,6) Intel Grand Ridge (Crestmont)
  * (0,6),(11,14) Intel Granite Rapids
  * Renamed 7/0/eax enh hardware feedback to just "Thread
    Director".
  * Added 7/1/eax instructions.
  * Added 0x12/0/eax SGX ENCLU EDECCSA flag.
  * Added 0x23 Architecture Performance Monitoring Extended leaf
    decoding.
  * Corrected AVX512IFMA description: integer FMA, not just FMA.
- Release 20220927
  * Added synth decoding for (10,15),(6,1) Raphael
  * Fixed title for AMD 0x8000001a leaf: Performance Optimization
    identifiers.</changelog>
  <changelog author="Valentin Lefebvre &lt;valentin.lefebvre@suse.com&gt;" date="1670241600">- Update to release 20221201
  * Clarified synth decoding for Intel Xeon D-1700.
  * Added uarch &amp; synth decoding for AMD 4800S Desktop Kit, based on
    instlatx64 sample.
  * Added uarch decoding for AMD Genoa A1, based on instlatx64 sample
  * Added uarch decoding for (0,6),(12,15) Emerald Rapids, from LX*.
  * Added synth &amp; uarch decoding for (10,15),(10,1) Bergamo.
  * Added 0x8000000a/edx bits: ROGPT, VNMI, IBS virtualization.
  * Added 0x8000001b/eax bit: IBS L3 miss filtering support.
  * Added 0x8000001f/eax bits: RMPQUERY instruction support,
    VMPL supervisor shadow stack support, VMGEXIT parameter support,
    virtual TOM MSR support, IBS virtual support for SEV-ES guests,
    SMT protection support, SVSM communication page MSR support,
    VIRT_RMPUPDATE &amp; VIRT_PSMASH MSR support.
  * Added 0x80000020/0/ecx bit: L3 range reservation support.
  * Added 0x80000021/eax bits: automatic IBRS,
    CPUID disable for non-privileged.
  * Added 0x80000022/eax bit: AMD LBR &amp; PMC freezing.
  * Added 0x80000022/ebx field: number of LBR stack entries.
  * Added 0x80000023 leaf: Multi-Key Encrypted Memory Capabilities.
  * Added 0x80000026 leaf: AMD Extended CPU Topology.
  * cpuid.c: use lseek64 and cpuset_setaffinity, Added 0x80000022/eax
    AMD LBR V2 flag, from LX*.</changelog>
  <changelog author="Dirk M&#xFC;ller &lt;dmueller@suse.com&gt;" date="1674907200">- updated to 20230120:
  * Intel's 13th Generation Core datasheet provides stepping names as
    well as numbers!  So:
  * cpuid.c: Added synth decoding for (0,6),(11,7) Raptor Lake B0 stepping.
  * cpuid.c: Added synth decoding for (0,6),(11,15) Raptor Lake C0
    steppings, and clarified case for unknown stepping.
  * cpuid.man: Added 743844: 13th Generation Core datasheet.
  * cpuid.c: Fixed (0,6)(12,15) synth typo: Emearld Rapids.
  * cpuid.c: Added 6/eax IA32_HW_FEEDBACK_THREAD_CONFIG bit 25.
  * cpuid.c: Added 7/0/edx SGX-KEYS: SGX attestation services.
  * cpuid.c: Clarified 7/0/edx IA32_MCU_OPT_CTRL SRBDS mitigation MSR.
  * cpuid.c: Clarified 7/0/edx IA32_TSX_FORCE_ABORT MSR.
  * cpuid.c: Added 7/1/edx CET_SSS: shadow stacks w/o page faults.
  * cpuid.c: Added several 7/2/edx bits.
  * cpuid.c: In 0xd/0/eax, corrected CET_U &amp; CET_S, which were IA32_XSS.
  * cpuid.c: In 0xd/0/eax, removed the IA32_XSS bits, which aren't
    relevant for XCR0.
  * cpuid.c: For 0xd/1/ecx, enumerate the IA32_XSS bits instead of a
    hex bitmask.
  * cpuid.c: For 0xd, added IA32_XSS PASID state (couple places).
  * cpuid.c: Renamed 0x1a: Native Model ID.
  * cpuid.c: Added synth &amp; uarch decoding for (0,6),(11,15) Raptor Lake
    from MSR_CPUID_table*.
  * cpuid.c: Added synth decoding for (0,6),(9,7),5 Pentium Gold G7400,
    based on instlatx64 sample.
  * cpuid.c: Added rudimentary synth decoding for future (0,6),(12,15)
    Emerald Rapids CPUs.
  * cpuid.c: Added 7/1/eax LASS: linear address space separation.
  * cpuid.c: Corrected 0x18/n/edx maximum number of addressible IDs, which
    should use minus-one notation.
  * cpuid.c: Certain leaves cannot be displayed correctly in isolation,
    i.e. without information about other leaves saved in the stash.  For
    example, the display for leaf 3 uses bits saved from leaf 1.  If the
  - l/--leaf option is used to restrict cpuid to reading only a single
    leaf, such leaves now are displayed as raw hex, rather than with
    incorrect information.  This is handled by passing a NULL stash to
    print_reg() and below, and by many new checks for a NULL stash.
  * cpuid.c: Updated cache associativity strings used in 0x80000006 and
    0x80000019 leaves to use value ranges, as in AMD docs.
  * cpuid.c: Fixed mistake in AMD L3 range reservation support: it's in
    0x80000020/0 register EBX, not ECX.
  * cpuid.c: Added 0x80000026/0/edx extended APIC ID.
  * cpuid.c: Added synth &amp; uarch decoding for (10,15),(1,1) Genoa, from
    AMD 57095 revision guide.
  * cpuid.man: Added AMD 57095 revision guides, and some older guides that
    I'd forgotten.</changelog>
  <changelog author="Egbert Eich &lt;eich@suse.com&gt;" date="1681473600">- Update to release 20230406:
  * Support APIC bit fields for the newest 4 topology layers:
    module, tile, die, die group.
  * Support leaf 0xb method for AMD/Hygon.
  * Added prelim Bergamo A1 stepping from sample.
  * Added AMX-COMPLEX instructions, UC-lock disable,
    non-contiguous 1s value support, event logging supported
    bitmap.
  * Update CPUID utility with new feature bits as documented in
    the AMD Processor Programming Reference for Family 19h and
    Model 11h: extended LVT offset fault cange, enhanced
    predictive store forwarding, FSRS, FSRC,
    FsGsKernelGsBaseNonSerializing, number of available UMC PMCs,
    bitmask representing active UMCs.
  * Added (synth) decoding for Sapphire Rapids D &amp; E0 steppings
  * Improved (synth) decoding for Scalable 3rd Gen Xeons to Ice
    Lake-SP, for Intel N-Series, for Raptor Lake-S/HX/P, for
    Raptor Lake-H/U/P.
  * Differentiate (synth) &amp; (uarch synth) for (0,6),(11,14)
    Alder Lake-N based on core type.
  * Differentiate Lakefield P-cores from Tremont E-cores.
  * Added (4th Gen) to the (synth) description of AMD EPYC Genoa.
  * Added (uarch synth) decoding for AMD Ryzen (Phoenix E0)
  * Added PkgType decoding for AMD Family 19h CPUs: Vermeer,
    Cezanne/Barcelo, Raphael, and Phoenix, based on their
    respective PPPRs.
  * Added Alder Lake Core names: i*-12000.
  * Decode Xen tsc mode.</changelog>
  <changelog author="Valentin Lefebvre &lt;valentin.lefebvre@suse.com&gt;" date="1687348800">- Update to release 20230614
  * Improved (synth) identification for Intel Xeon Scalable (3rd
    Gen) (Cooper Lake A0), Intel Xeon D-1700/2700 (Ice Lake-D),
    Intel Pentium Gold 8500 series, pure Atom x7000E, Atom C1100
    Arizona Beach.
  * Made the (simple synth) fields non-default. The (simple synth)
    fields still are available, but only with the -S/--simple
    option.
- Update to release 20230505
  * Fixed CPU counts for higher levels
    not dividing out counts from lower levels.
  * Differentiate Core i3-N300 N-Series from ordinary N-Series.
  * Added hypervisor+4/eax bit 21: use hypercalls for MMIO config
    space I/O, based on LX*.
  * Added (synth) decoding for Xeon W version of Sapphire Rapids,
    Meteor Lake-M B0.
  * Added (synth) &amp; (uarch synth) Emerald Rapids family: Raptor
    Cove, and Granite Rapids family: Redwood Cove.</changelog>
</package>
<package pkgid="5b6a6a7aa291984cee706d49304495455f91bc656a8039702f785dd05386ef4f7fa324389cd5bde32c021b0341130478a1d5503bf4b22afb9dc1845e72e94b62" name="cpuid-debugsource" arch="i586">
  <version epoch="0" ver="20230614" rel="2.33"/>
  <changelog author="Andreas Stieger &lt;andreas.stieger@gmx.de&gt;" date="1588075200">- update to 20200427:
  * Add synth decoding for AMD Steppe Eagle/Crowned Eagle
    (Puma 2014 G-Series), based on instlatx64 sample
  * Add 7/0/edx SERIALIZE &amp; TSXLDTRK bit descriptions
  * Add 0xf/1/eax Counter width &amp; overflow flag
  * Add 0x10/3/ecx per-thread MBA controls flag
  * Add 0x8000001f fields
  * Add AMD 24594 &amp; 40332 docs
  * Correct field lengths in 14/0 and 14/1 subleafs so that
    columns line up
  * Add CC150 (Coffee Lake R0) synth decoding, based on
    instlatx64 example
  * Add Jasper Lake A0 stepping (from Coreboot*)
  * Update 1/ebx "cpu count" to modern terminology: "maximum
    addressible IDs for CPUs in pkg" to avoid user confusion
  * Update 4/eax CPU &amp; core count terminology in the same way</changelog>
  <changelog author="Josef M&#xF6;llers &lt;josef.moellers@suse.com&gt;" date="1602158400">- Update to 20201006:
  Added "Sapphire Rapids", "Golden Cove", "Rocket Lake", "Cato",
  14nm "Zen", "Tiger Lake-U B0", "Elkhart Lake B0", "Alder Lake",
  "Comet Lake", "Picasso A1", "Renoir A1", "Zhaoxin KaiXian KX-6000",
  as well as some additional decoding of supported features.
  [cpuid-20201006.src.tar.gz, jsc#sle-13189]</changelog>
  <changelog author="Andreas Stieger &lt;andreas.stieger@gmx.de&gt;" date="1636977600">- update to 20211114:
  * Many updated and added identified CPU models and variants
  * Updated hypervisor support</changelog>
  <changelog author="Andreas Stieger &lt;andreas.stieger@gmx.de&gt;" date="1645704000">- update to 20220224:
  * Support for AMD Rembrandt E1
  * Add hypervisor+4/eax (Xen) expanded destination id bit
  * Correction for Alder Lake, Rocket Lake decoding
  * Multiple detection and decodings updated</changelog>
  <changelog author="Jan Engelhardt &lt;jengelh@inai.de&gt;" date="1660392000">- Update to release 20220812
  * Corrected (synth) decoding for (0,6),(8,6) Intel Snow
    Ridge/Parker Ridge.
  * Added 8000000a/edx X2AVIC flag
  * Generalized (0,6),(8,14),9,YP stepping case to include
    Pentium 4425Y, from instlatx64 sample.
  * Added support for hypervisor+3/ecx (Microsoft) flags.</changelog>
  <changelog author="Valentin Lefebvre &lt;valentin.lefebvre@suse.com&gt;" date="1665662400">- Update to release 20221003
  * Added synth decoding for AMD Ryzen (Phoenix E0, Storm Peak A1)
  * Added synth &amp; uarch synth decoding for
  * (0,6),(11,5) Intel Meteor Lake
  * (0,6),(11,6) Intel Grand Ridge (Crestmont)
  * (0,6),(11,14) Intel Granite Rapids
  * Renamed 7/0/eax enh hardware feedback to just "Thread
    Director".
  * Added 7/1/eax instructions.
  * Added 0x12/0/eax SGX ENCLU EDECCSA flag.
  * Added 0x23 Architecture Performance Monitoring Extended leaf
    decoding.
  * Corrected AVX512IFMA description: integer FMA, not just FMA.
- Release 20220927
  * Added synth decoding for (10,15),(6,1) Raphael
  * Fixed title for AMD 0x8000001a leaf: Performance Optimization
    identifiers.</changelog>
  <changelog author="Valentin Lefebvre &lt;valentin.lefebvre@suse.com&gt;" date="1670241600">- Update to release 20221201
  * Clarified synth decoding for Intel Xeon D-1700.
  * Added uarch &amp; synth decoding for AMD 4800S Desktop Kit, based on
    instlatx64 sample.
  * Added uarch decoding for AMD Genoa A1, based on instlatx64 sample
  * Added uarch decoding for (0,6),(12,15) Emerald Rapids, from LX*.
  * Added synth &amp; uarch decoding for (10,15),(10,1) Bergamo.
  * Added 0x8000000a/edx bits: ROGPT, VNMI, IBS virtualization.
  * Added 0x8000001b/eax bit: IBS L3 miss filtering support.
  * Added 0x8000001f/eax bits: RMPQUERY instruction support,
    VMPL supervisor shadow stack support, VMGEXIT parameter support,
    virtual TOM MSR support, IBS virtual support for SEV-ES guests,
    SMT protection support, SVSM communication page MSR support,
    VIRT_RMPUPDATE &amp; VIRT_PSMASH MSR support.
  * Added 0x80000020/0/ecx bit: L3 range reservation support.
  * Added 0x80000021/eax bits: automatic IBRS,
    CPUID disable for non-privileged.
  * Added 0x80000022/eax bit: AMD LBR &amp; PMC freezing.
  * Added 0x80000022/ebx field: number of LBR stack entries.
  * Added 0x80000023 leaf: Multi-Key Encrypted Memory Capabilities.
  * Added 0x80000026 leaf: AMD Extended CPU Topology.
  * cpuid.c: use lseek64 and cpuset_setaffinity, Added 0x80000022/eax
    AMD LBR V2 flag, from LX*.</changelog>
  <changelog author="Dirk M&#xFC;ller &lt;dmueller@suse.com&gt;" date="1674907200">- updated to 20230120:
  * Intel's 13th Generation Core datasheet provides stepping names as
    well as numbers!  So:
  * cpuid.c: Added synth decoding for (0,6),(11,7) Raptor Lake B0 stepping.
  * cpuid.c: Added synth decoding for (0,6),(11,15) Raptor Lake C0
    steppings, and clarified case for unknown stepping.
  * cpuid.man: Added 743844: 13th Generation Core datasheet.
  * cpuid.c: Fixed (0,6)(12,15) synth typo: Emearld Rapids.
  * cpuid.c: Added 6/eax IA32_HW_FEEDBACK_THREAD_CONFIG bit 25.
  * cpuid.c: Added 7/0/edx SGX-KEYS: SGX attestation services.
  * cpuid.c: Clarified 7/0/edx IA32_MCU_OPT_CTRL SRBDS mitigation MSR.
  * cpuid.c: Clarified 7/0/edx IA32_TSX_FORCE_ABORT MSR.
  * cpuid.c: Added 7/1/edx CET_SSS: shadow stacks w/o page faults.
  * cpuid.c: Added several 7/2/edx bits.
  * cpuid.c: In 0xd/0/eax, corrected CET_U &amp; CET_S, which were IA32_XSS.
  * cpuid.c: In 0xd/0/eax, removed the IA32_XSS bits, which aren't
    relevant for XCR0.
  * cpuid.c: For 0xd/1/ecx, enumerate the IA32_XSS bits instead of a
    hex bitmask.
  * cpuid.c: For 0xd, added IA32_XSS PASID state (couple places).
  * cpuid.c: Renamed 0x1a: Native Model ID.
  * cpuid.c: Added synth &amp; uarch decoding for (0,6),(11,15) Raptor Lake
    from MSR_CPUID_table*.
  * cpuid.c: Added synth decoding for (0,6),(9,7),5 Pentium Gold G7400,
    based on instlatx64 sample.
  * cpuid.c: Added rudimentary synth decoding for future (0,6),(12,15)
    Emerald Rapids CPUs.
  * cpuid.c: Added 7/1/eax LASS: linear address space separation.
  * cpuid.c: Corrected 0x18/n/edx maximum number of addressible IDs, which
    should use minus-one notation.
  * cpuid.c: Certain leaves cannot be displayed correctly in isolation,
    i.e. without information about other leaves saved in the stash.  For
    example, the display for leaf 3 uses bits saved from leaf 1.  If the
  - l/--leaf option is used to restrict cpuid to reading only a single
    leaf, such leaves now are displayed as raw hex, rather than with
    incorrect information.  This is handled by passing a NULL stash to
    print_reg() and below, and by many new checks for a NULL stash.
  * cpuid.c: Updated cache associativity strings used in 0x80000006 and
    0x80000019 leaves to use value ranges, as in AMD docs.
  * cpuid.c: Fixed mistake in AMD L3 range reservation support: it's in
    0x80000020/0 register EBX, not ECX.
  * cpuid.c: Added 0x80000026/0/edx extended APIC ID.
  * cpuid.c: Added synth &amp; uarch decoding for (10,15),(1,1) Genoa, from
    AMD 57095 revision guide.
  * cpuid.man: Added AMD 57095 revision guides, and some older guides that
    I'd forgotten.</changelog>
  <changelog author="Egbert Eich &lt;eich@suse.com&gt;" date="1681473600">- Update to release 20230406:
  * Support APIC bit fields for the newest 4 topology layers:
    module, tile, die, die group.
  * Support leaf 0xb method for AMD/Hygon.
  * Added prelim Bergamo A1 stepping from sample.
  * Added AMX-COMPLEX instructions, UC-lock disable,
    non-contiguous 1s value support, event logging supported
    bitmap.
  * Update CPUID utility with new feature bits as documented in
    the AMD Processor Programming Reference for Family 19h and
    Model 11h: extended LVT offset fault cange, enhanced
    predictive store forwarding, FSRS, FSRC,
    FsGsKernelGsBaseNonSerializing, number of available UMC PMCs,
    bitmask representing active UMCs.
  * Added (synth) decoding for Sapphire Rapids D &amp; E0 steppings
  * Improved (synth) decoding for Scalable 3rd Gen Xeons to Ice
    Lake-SP, for Intel N-Series, for Raptor Lake-S/HX/P, for
    Raptor Lake-H/U/P.
  * Differentiate (synth) &amp; (uarch synth) for (0,6),(11,14)
    Alder Lake-N based on core type.
  * Differentiate Lakefield P-cores from Tremont E-cores.
  * Added (4th Gen) to the (synth) description of AMD EPYC Genoa.
  * Added (uarch synth) decoding for AMD Ryzen (Phoenix E0)
  * Added PkgType decoding for AMD Family 19h CPUs: Vermeer,
    Cezanne/Barcelo, Raphael, and Phoenix, based on their
    respective PPPRs.
  * Added Alder Lake Core names: i*-12000.
  * Decode Xen tsc mode.</changelog>
  <changelog author="Valentin Lefebvre &lt;valentin.lefebvre@suse.com&gt;" date="1687348800">- Update to release 20230614
  * Improved (synth) identification for Intel Xeon Scalable (3rd
    Gen) (Cooper Lake A0), Intel Xeon D-1700/2700 (Ice Lake-D),
    Intel Pentium Gold 8500 series, pure Atom x7000E, Atom C1100
    Arizona Beach.
  * Made the (simple synth) fields non-default. The (simple synth)
    fields still are available, but only with the -S/--simple
    option.
- Update to release 20230505
  * Fixed CPU counts for higher levels
    not dividing out counts from lower levels.
  * Differentiate Core i3-N300 N-Series from ordinary N-Series.
  * Added hypervisor+4/eax bit 21: use hypercalls for MMIO config
    space I/O, based on LX*.
  * Added (synth) decoding for Xeon W version of Sapphire Rapids,
    Meteor Lake-M B0.
  * Added (synth) &amp; (uarch synth) Emerald Rapids family: Raptor
    Cove, and Granite Rapids family: Redwood Cove.</changelog>
</package>
<package pkgid="81be28bc4121fe7e6d08b988c45c6306be6c1723f2a8f037caacaf1d232bba35d8eae541dd3a89924a12546217d79c921f736e05c5210a52ae53f121e9435ba1" name="cpuid-debugsource" arch="x86_64">
  <version epoch="0" ver="20230614" rel="2.33"/>
  <changelog author="Andreas Stieger &lt;andreas.stieger@gmx.de&gt;" date="1588075200">- update to 20200427:
  * Add synth decoding for AMD Steppe Eagle/Crowned Eagle
    (Puma 2014 G-Series), based on instlatx64 sample
  * Add 7/0/edx SERIALIZE &amp; TSXLDTRK bit descriptions
  * Add 0xf/1/eax Counter width &amp; overflow flag
  * Add 0x10/3/ecx per-thread MBA controls flag
  * Add 0x8000001f fields
  * Add AMD 24594 &amp; 40332 docs
  * Correct field lengths in 14/0 and 14/1 subleafs so that
    columns line up
  * Add CC150 (Coffee Lake R0) synth decoding, based on
    instlatx64 example
  * Add Jasper Lake A0 stepping (from Coreboot*)
  * Update 1/ebx "cpu count" to modern terminology: "maximum
    addressible IDs for CPUs in pkg" to avoid user confusion
  * Update 4/eax CPU &amp; core count terminology in the same way</changelog>
  <changelog author="Josef M&#xF6;llers &lt;josef.moellers@suse.com&gt;" date="1602158400">- Update to 20201006:
  Added "Sapphire Rapids", "Golden Cove", "Rocket Lake", "Cato",
  14nm "Zen", "Tiger Lake-U B0", "Elkhart Lake B0", "Alder Lake",
  "Comet Lake", "Picasso A1", "Renoir A1", "Zhaoxin KaiXian KX-6000",
  as well as some additional decoding of supported features.
  [cpuid-20201006.src.tar.gz, jsc#sle-13189]</changelog>
  <changelog author="Andreas Stieger &lt;andreas.stieger@gmx.de&gt;" date="1636977600">- update to 20211114:
  * Many updated and added identified CPU models and variants
  * Updated hypervisor support</changelog>
  <changelog author="Andreas Stieger &lt;andreas.stieger@gmx.de&gt;" date="1645704000">- update to 20220224:
  * Support for AMD Rembrandt E1
  * Add hypervisor+4/eax (Xen) expanded destination id bit
  * Correction for Alder Lake, Rocket Lake decoding
  * Multiple detection and decodings updated</changelog>
  <changelog author="Jan Engelhardt &lt;jengelh@inai.de&gt;" date="1660392000">- Update to release 20220812
  * Corrected (synth) decoding for (0,6),(8,6) Intel Snow
    Ridge/Parker Ridge.
  * Added 8000000a/edx X2AVIC flag
  * Generalized (0,6),(8,14),9,YP stepping case to include
    Pentium 4425Y, from instlatx64 sample.
  * Added support for hypervisor+3/ecx (Microsoft) flags.</changelog>
  <changelog author="Valentin Lefebvre &lt;valentin.lefebvre@suse.com&gt;" date="1665662400">- Update to release 20221003
  * Added synth decoding for AMD Ryzen (Phoenix E0, Storm Peak A1)
  * Added synth &amp; uarch synth decoding for
  * (0,6),(11,5) Intel Meteor Lake
  * (0,6),(11,6) Intel Grand Ridge (Crestmont)
  * (0,6),(11,14) Intel Granite Rapids
  * Renamed 7/0/eax enh hardware feedback to just "Thread
    Director".
  * Added 7/1/eax instructions.
  * Added 0x12/0/eax SGX ENCLU EDECCSA flag.
  * Added 0x23 Architecture Performance Monitoring Extended leaf
    decoding.
  * Corrected AVX512IFMA description: integer FMA, not just FMA.
- Release 20220927
  * Added synth decoding for (10,15),(6,1) Raphael
  * Fixed title for AMD 0x8000001a leaf: Performance Optimization
    identifiers.</changelog>
  <changelog author="Valentin Lefebvre &lt;valentin.lefebvre@suse.com&gt;" date="1670241600">- Update to release 20221201
  * Clarified synth decoding for Intel Xeon D-1700.
  * Added uarch &amp; synth decoding for AMD 4800S Desktop Kit, based on
    instlatx64 sample.
  * Added uarch decoding for AMD Genoa A1, based on instlatx64 sample
  * Added uarch decoding for (0,6),(12,15) Emerald Rapids, from LX*.
  * Added synth &amp; uarch decoding for (10,15),(10,1) Bergamo.
  * Added 0x8000000a/edx bits: ROGPT, VNMI, IBS virtualization.
  * Added 0x8000001b/eax bit: IBS L3 miss filtering support.
  * Added 0x8000001f/eax bits: RMPQUERY instruction support,
    VMPL supervisor shadow stack support, VMGEXIT parameter support,
    virtual TOM MSR support, IBS virtual support for SEV-ES guests,
    SMT protection support, SVSM communication page MSR support,
    VIRT_RMPUPDATE &amp; VIRT_PSMASH MSR support.
  * Added 0x80000020/0/ecx bit: L3 range reservation support.
  * Added 0x80000021/eax bits: automatic IBRS,
    CPUID disable for non-privileged.
  * Added 0x80000022/eax bit: AMD LBR &amp; PMC freezing.
  * Added 0x80000022/ebx field: number of LBR stack entries.
  * Added 0x80000023 leaf: Multi-Key Encrypted Memory Capabilities.
  * Added 0x80000026 leaf: AMD Extended CPU Topology.
  * cpuid.c: use lseek64 and cpuset_setaffinity, Added 0x80000022/eax
    AMD LBR V2 flag, from LX*.</changelog>
  <changelog author="Dirk M&#xFC;ller &lt;dmueller@suse.com&gt;" date="1674907200">- updated to 20230120:
  * Intel's 13th Generation Core datasheet provides stepping names as
    well as numbers!  So:
  * cpuid.c: Added synth decoding for (0,6),(11,7) Raptor Lake B0 stepping.
  * cpuid.c: Added synth decoding for (0,6),(11,15) Raptor Lake C0
    steppings, and clarified case for unknown stepping.
  * cpuid.man: Added 743844: 13th Generation Core datasheet.
  * cpuid.c: Fixed (0,6)(12,15) synth typo: Emearld Rapids.
  * cpuid.c: Added 6/eax IA32_HW_FEEDBACK_THREAD_CONFIG bit 25.
  * cpuid.c: Added 7/0/edx SGX-KEYS: SGX attestation services.
  * cpuid.c: Clarified 7/0/edx IA32_MCU_OPT_CTRL SRBDS mitigation MSR.
  * cpuid.c: Clarified 7/0/edx IA32_TSX_FORCE_ABORT MSR.
  * cpuid.c: Added 7/1/edx CET_SSS: shadow stacks w/o page faults.
  * cpuid.c: Added several 7/2/edx bits.
  * cpuid.c: In 0xd/0/eax, corrected CET_U &amp; CET_S, which were IA32_XSS.
  * cpuid.c: In 0xd/0/eax, removed the IA32_XSS bits, which aren't
    relevant for XCR0.
  * cpuid.c: For 0xd/1/ecx, enumerate the IA32_XSS bits instead of a
    hex bitmask.
  * cpuid.c: For 0xd, added IA32_XSS PASID state (couple places).
  * cpuid.c: Renamed 0x1a: Native Model ID.
  * cpuid.c: Added synth &amp; uarch decoding for (0,6),(11,15) Raptor Lake
    from MSR_CPUID_table*.
  * cpuid.c: Added synth decoding for (0,6),(9,7),5 Pentium Gold G7400,
    based on instlatx64 sample.
  * cpuid.c: Added rudimentary synth decoding for future (0,6),(12,15)
    Emerald Rapids CPUs.
  * cpuid.c: Added 7/1/eax LASS: linear address space separation.
  * cpuid.c: Corrected 0x18/n/edx maximum number of addressible IDs, which
    should use minus-one notation.
  * cpuid.c: Certain leaves cannot be displayed correctly in isolation,
    i.e. without information about other leaves saved in the stash.  For
    example, the display for leaf 3 uses bits saved from leaf 1.  If the
  - l/--leaf option is used to restrict cpuid to reading only a single
    leaf, such leaves now are displayed as raw hex, rather than with
    incorrect information.  This is handled by passing a NULL stash to
    print_reg() and below, and by many new checks for a NULL stash.
  * cpuid.c: Updated cache associativity strings used in 0x80000006 and
    0x80000019 leaves to use value ranges, as in AMD docs.
  * cpuid.c: Fixed mistake in AMD L3 range reservation support: it's in
    0x80000020/0 register EBX, not ECX.
  * cpuid.c: Added 0x80000026/0/edx extended APIC ID.
  * cpuid.c: Added synth &amp; uarch decoding for (10,15),(1,1) Genoa, from
    AMD 57095 revision guide.
  * cpuid.man: Added AMD 57095 revision guides, and some older guides that
    I'd forgotten.</changelog>
  <changelog author="Egbert Eich &lt;eich@suse.com&gt;" date="1681473600">- Update to release 20230406:
  * Support APIC bit fields for the newest 4 topology layers:
    module, tile, die, die group.
  * Support leaf 0xb method for AMD/Hygon.
  * Added prelim Bergamo A1 stepping from sample.
  * Added AMX-COMPLEX instructions, UC-lock disable,
    non-contiguous 1s value support, event logging supported
    bitmap.
  * Update CPUID utility with new feature bits as documented in
    the AMD Processor Programming Reference for Family 19h and
    Model 11h: extended LVT offset fault cange, enhanced
    predictive store forwarding, FSRS, FSRC,
    FsGsKernelGsBaseNonSerializing, number of available UMC PMCs,
    bitmask representing active UMCs.
  * Added (synth) decoding for Sapphire Rapids D &amp; E0 steppings
  * Improved (synth) decoding for Scalable 3rd Gen Xeons to Ice
    Lake-SP, for Intel N-Series, for Raptor Lake-S/HX/P, for
    Raptor Lake-H/U/P.
  * Differentiate (synth) &amp; (uarch synth) for (0,6),(11,14)
    Alder Lake-N based on core type.
  * Differentiate Lakefield P-cores from Tremont E-cores.
  * Added (4th Gen) to the (synth) description of AMD EPYC Genoa.
  * Added (uarch synth) decoding for AMD Ryzen (Phoenix E0)
  * Added PkgType decoding for AMD Family 19h CPUs: Vermeer,
    Cezanne/Barcelo, Raphael, and Phoenix, based on their
    respective PPPRs.
  * Added Alder Lake Core names: i*-12000.
  * Decode Xen tsc mode.</changelog>
  <changelog author="Valentin Lefebvre &lt;valentin.lefebvre@suse.com&gt;" date="1687348800">- Update to release 20230614
  * Improved (synth) identification for Intel Xeon Scalable (3rd
    Gen) (Cooper Lake A0), Intel Xeon D-1700/2700 (Ice Lake-D),
    Intel Pentium Gold 8500 series, pure Atom x7000E, Atom C1100
    Arizona Beach.
  * Made the (simple synth) fields non-default. The (simple synth)
    fields still are available, but only with the -S/--simple
    option.
- Update to release 20230505
  * Fixed CPU counts for higher levels
    not dividing out counts from lower levels.
  * Differentiate Core i3-N300 N-Series from ordinary N-Series.
  * Added hypervisor+4/eax bit 21: use hypercalls for MMIO config
    space I/O, based on LX*.
  * Added (synth) decoding for Xeon W version of Sapphire Rapids,
    Meteor Lake-M B0.
  * Added (synth) &amp; (uarch synth) Emerald Rapids family: Raptor
    Cove, and Granite Rapids family: Redwood Cove.</changelog>
</package>
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  <version epoch="0" ver="0.7.10~git0.54f3613" rel="4.70"/>
  <changelog author="Jeff Mahoney &lt;jeffm@suse.com&gt; - 0.7.10" date="1716465600">- Initial packaging.</changelog>
  <changelog author="Jeff Mahoney &lt;jeffm@suse.com&gt;" date="1716897600">- Add build flags to make Nvidia support optional</changelog>
  <changelog author="Jeff Mahoney &lt;jeffm@suse.com&gt;" date="1716897601">- Require clang version capable of building BTF</changelog>
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  <changelog author="Jeff Mahoney &lt;jeffm@suse.com&gt; - 0.7.10" date="1716465600">- Initial packaging.</changelog>
  <changelog author="Jeff Mahoney &lt;jeffm@suse.com&gt;" date="1716897600">- Add build flags to make Nvidia support optional</changelog>
  <changelog author="Jeff Mahoney &lt;jeffm@suse.com&gt;" date="1716897601">- Require clang version capable of building BTF</changelog>
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